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Nanusens Limited

Nanusens Limited

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Until now, MEMS sensors are all created using expensive proprietary processes to build the structure on the top of a CMOS wafer. Each design of MEMS sensor needs a unique process to make that takes 5-7 years to perfect and there are no economies of scale or ability to rapidly ramp production. Each MEMS sensor then needs a control chip paired with it resulting in a multi-chip package of typically 4mm3. Nanusens’ multi-patent pending technology enables it to create nanosensors inside the CMOS layers using standard CMOS processes within the same production flow as the rest of the chip production. This innovative approach reduces the size and cost of the sensors as it benefits from the vast economies of scale of using giant CMOS fabs. We use 0.18-micron CMOS technology as it is a well-established, high volume technology used by most fabs giving us the freedom to use any fab. This is important as it means that we can rapidly ramp production into the multi-millions when required. Our feature sizes are sub-micron at 0.3 microns. By way of contrast, MEMS feature sizes are typically 3 micron – some ten times larger. The Inter Metal Dielectric (IMD) is etched away through the pad openings in the passivation layer using vapour HF (vHF) to create the nanosensor structures. The holes are then sealed and the chip packaged as necessary. As only standard CMOS processes with minimal post-processing are used, they can have high yields similar to CMOS devices. This also means that the production is fab-independent.

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